module booth(
iclk, // input clock
iReset, // reset signal
iReady, // indicates inputs are ready
oDone, // indicates that the result is ready
iMultiplier, // 8-bit multiplier [7:0]
iMultiplicand, // 8-bit multiplicand [7:0]
oProduct // 16-bit product [15:0]
);



input [7:0] iMultiplier, iMultiplicand;
input iclk, iReset, iReady;
output [7:0] oDone;
output [15:0] oProduct;


reg [7:0] A;
reg [7:0] L;
reg Q, a, b;
reg [16:0] P;
reg [15:0] oProduct;
reg [7:0] oDone;
wire [7:0] sum1, sum2;
wire cout;
wire [7:0] muxout;

//reset//

initial begin
A[7:0] = 8'b00000000;
L[7:0] = iMultiplier[7:0];
Q = 1'b 0;
oDone[7:0] = 8'b10000000;
a = 1'b 0;
b = 1'b 1;
end

addsub add1(A[7:0],iMultiplicand[7:0],a,sum1[7:0],cout);
addsub sub1(A[7:0],iMultiplicand[7:0],b,sum2[7:0],cout);

mux4to1 mux1(A[7:0],sum1[7:0],sum2[7:0],A[7:0],Q,L[0],muxout[7:0]);
 
always @(posedge iclk) begin
A[7:0] = muxout[7:0];
P[16:0] = {A[7:0], L[7:0],Q};
oProduct[14:0] = P[16:2];
oProduct[15] = 1'b 0;
L[0] = oProduct[0];
A[7:0] = oProduct[15:8];
L[7:0] = oProduct[7:0];
oDone[6:0] = oDone[7:1];

end

endmodule
